View HCPL-J454-400E_7193179.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features ? short propagation delays for ttl and ipm applications ? 15 kv/s minimum common mode transient immu- nity at v cm = 1500 v for ttl/load drive ? high ctr at t a = 25c >25% for hcpl-4504/0454 >23% for hcnw4504 >19% for hcpl-j454 ? electrical speci? cations for common ipm applications ? ttl compatible ? open collector output ? safety approval: ul recognized C 3750 v rms/1min. for hcpl-4504/0454/j454 C 5000 v rms/1min. for hcpl-4504 option 020 and hcnw4504 csa approved iec/en/din en 60747-5-2 approved C v iorm = 560 vpeak for hcpl-0454 option 060 C v iorm = 630 vpeak for hcpl-4504 option 060 C v iorm = 891 vpeak for hcpl-j454 C v iorm = 1414 vpeak for hcnw4504 applications ? inverter circuits and intelligent power module (ipm) interfacing: high common mode transient immunity (> 10 kv/s for an ipm load/drive) and (t plh - t phl ) speci? ed (see power inverter dead time section) ? line receivers: short propagation delays and low in- put-output capacitance ? high speed logic ground isolation: ttl/ttl, ttl/ cmos, ttl/lsttl ? replaces pulse transformers: save board space and weight ? analog signal ground isolation: integrated photode- tector provides improved linearity over phototransis- tors a 0.1 f bypass capacitor between pins 5 and 8 is recommended. 7 1 2 3 4 5 6 8 nc anode cathode nc v cc nc v o gnd truth table led on off v o low high description the hcpl-4504 and hcpl-0454 contain a gaasp led while the hcpl-j454 and hcnw4504 contain an algaas led. the led is optically coupled to an integrated high gain photo detector. the hcpl-4504 series has short propagation delays and high ctr. the hcpl-4504 series also has a guaranteed propagation delay di? erence (t plh -t phl ). these features make the hcpl-4504 series an excellent solution to ipm inverter dead time and other switching problems. the ctr, propagation delay, and cmr are speci? ed both for ttl and ipm conditions which are provided for ease of application. these single channel, diode-transistor opto- couplers are available in 8-pin dip, so-8, and widebody package con? gurations. an insulating layer between a led and an integrated photodetector provide electrical insulation between input and output. separate connec- tions for the photodiode bias and output-transistor col- lector increase the speed up to a hundred times that of a conventional phototransistor coupler by reducing the base collector capacitance. functional diagram hcpl-4504/j454/0454, hcnw4504 high cmr, high speed optocouplers data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product schematic i f shield 8 6 5 gnd v cc 2 3 v o i cc v f i o anode cathode +
2 ordering information hcpl-0454, hcpl-4504 and hcpl-j454 are ul recognized with 3750 vrms for 1 minute per ul1577. hcnw4504 is ul recognized with 5000 vrms for 1 minute per ul1577. hcpl-0454, hcpl-4504, hcpl-j454 and hcnw4504 are approved under csa component acceptance notice #5, file ca 88324. part number option package surface mount gull wing tape & reel ul 1577 5000 vrms/ 1 minute rating iec/en/din en 60747-5-2 quantity rohs compliant non rohs compliant hcpl-4504 -000e no option 300 mil dip-8 50 per tube -300e #300 x x 50 per tube -500e #500 x x x 1000 per reel -020e #020 x 50 per tube -320e #320 x x x 50 per tube -520e #520 x x x x 1000 per reel -060e #060 x 50 per tube -360e #360 x x x 50 per tube -560e #560 x x x x 1000 per reel hcpl-j454 -000e no option 300 mil dip-8 x 50 per tube -300e #300 x x x 50 per tube -400e na x x x 50 per tube -500e #500 x x x x 1000 per reel -600e na x x x x 750 per reel hcpl-0454 -000e no option so-8 x 100 per tube -500e #500 x x 1500 per reel -060e #060 x x 100 per tube -560e #560 x x x 1500 per reel hcnw4504 -000e no option 400 mil widebody dip-8 x x 42 per tube -300e #300 x x x x 42 per tube -500e #500 x x x x x 750 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: hcpl-4504-560e to order product of 300 mil dip gull wing surface mount package in tape and reel packaging with iec/en/din en 60747-5-2 safety approval and rohs compliant. example 2: hcpl-4504 to order product of 300 mil dip package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since july 15, 2001 and rohs compliant will use Cxxxe.
3 package outline drawings hcpl-4504 outline drawing hcpl-4504 gull wing surface mount option 300 outline drawing 1.080 ?0.320 (0.043 ?0.013) 2.54 ?0.25 (0.100 ?0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. 5?typ. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 ?0.25 (0.300 ?0.010) 6.35 ?0.25 (0.250 ?0.010) 9.65 ?0.25 (0.380 ?0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxz yyww date code dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 option code* ul recognition ur type number * marking code letter for option numbers "l" = option 020 "v" = option 060 option numbers 300 and 500 not marked. note: floating lead protrusion is 0.25 mm (10 mils) max. 3.56 ?0.13 (0.140 ?0.005) 0.635 ?0.25 (0.025 ?0.010) 12?nom. 9.65 ?0.25 (0.380 ?0.010) 0.635 ?0.130 (0.025 ?0.005) 7.62 ?0.25 (0.300 ?0.010) 5 6 7 8 4 3 2 1 9.65 ?0.25 (0.380 ?0.010) 6.350 ?0.25 (0.250 ?0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 ?0.320 (0.043 ?0.013) 3.56 ?0.13 (0.140 ?0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002)
4 package outline drawings hcpl-j454 outline drawing hcpl-j454 gull wing surface mount option 300 outline drawing 1.080 ?0.320 (0.043 ?0.013) 2.54 ?0.25 (0.100 ?0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. 5 typ. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 ?0.25 (0.300 ?0.010) 6.35 ?0.25 (0.250 ?0.010) 9.80 ?0.25 (0.386 ?0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxx yyww date code dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 ul recognition ur type number option numbers 300 and 500 not marked. note: floating lead protrusion is 0.5 mm (20 mils) max. 3.56 ?0.13 (0.140 ?0.005) 0.635 ?0.25 (0.025 ?0.010) 12?nom. 9.65 ?0.25 (0.380 ?0.010) 0.635 ?0.130 (0.025 ?0.005) 7.62 ?0.25 (0.300 ?0.010) 5 6 7 8 4 3 2 1 9.80 ?0.25 (0.386 ?0.010) 6.350 ?0.25 (0.250 ?0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 ?0.320 (0.043 ?0.013) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) note: floating lead protrusion is 0.5 mm (20 mils) max. 3.56 ?0.13 (0.140 ?0.005)
5 HCPL-J454-400E/600e widelead gullwing surface mount outline drawing hcpl-0454 outline drawing (8-pin small outline package) xxx yww 8765 4 3 2 1 5.994 0.203 (0.236 0.008) 3.937 0.127 (0.155 0.005) 0.406 0.076 (0.016 0.003) 1.270 (0.050) bsc 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005) 1.524 (0.060) 45 x 0.432 (0.017) 0.228 0.025 (0.009 0.001) type number (last 3 digits) date code 0.305 (0.012) min. total package length (inclusive of mold flash) 5.207 0.254 (0.205 0.010) dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches) max. note: floating lead protrusion is 0.15 mm (6 mils) max. 0.203 0.102 (0.008 0.004) 7 pin one 0 ~ 7 * * 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) land pattern recommendation [0.65] 0.025 max 0.250 0.010 6.35 0.25 0.386 0.010 9.80 0.25 max. [1.19] 0.047 0.140 0.005 3.56 0.13 0.100 bsc 2.54 0.043 0.013 [1.080] 0.320 dimensions in [millimeters] inches option numbers 400 and 600 not marked. note: floating lead protrusion is 0.5 mm (20 mils) max. lead coplanarity maximum: [0.102] 0.004 land pattern recommendation 0.460 0.010 [11.75 0.25] [0.406] 0.016 [0.152] 0.006 0.025 0.010 0.625 0.254 0.300 0.020 7.62 0.51 [0.33] 0.013 [0.20] 0.008 30 nom. 0.040 1.016 0.508 12.9 0.08 2.0 0.050 1.27 a xxxx yyww date code ur type number ul recognition
6 hcnw4504 outline drawing (8-pin widebody package) 5 6 7 8 4 3 2 1 11.15 ?0.15 (0.442 ?0.006) 1.78 ?0.15 (0.070 ?0.006) 5.10 (0.201) max. 1.55 (0.061) max. 2.54 (0.100) typ. dimensions in millimeters (inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 7?typ. 0.254 + 0.076 - 0.0051 (0.010 + 0.003) - 0.002) 11.00 (0.433) 9.00 ?0.15 (0.354 ?0.006) max. 10.16 (0.400) typ. a hcnwxxxx yyww date code type number 0.51 (0.021) min. 0.40 (0.016) 0.56 (0.022) 3.10 (0.122) 3.90 (0.154) hcnw4504 gull wing surface mount option 300 outline drawing 1.00 ?0.15 (0.039 ?0.006) 7?nom. 12.30 ?0.30 (0.484 ?0.012) 0.75 ?0.25 (0.030 ?0.010) 11.00 (0.433) 5 6 7 8 4 3 2 1 11.15 ?0.15 (0.442 ?0.006) 9.00 ?0.15 (0.354 ?0.006) 1.3 (0.051) 13.56 (0.534) 2.29 (0.09) land pattern recommendation 1.78 ?0.15 (0.070 ?0.006) 4.00 (0.158) max. 1.55 (0.061) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 0.254 + 0.076 - 0.0051 (0.010 + 0.003) - 0.002) max.
7 solder re? ow temperature pro? le recommended pb-free ir pro? le 0 ti me (seconds) t empera t ure ( c) 200 1 00 50 1 50 1 00 200 250 300 0 30 sec . 50 sec . 30 sec . 1 60 c 1 40 c 1 50 c pea k t emp . 245 c pea k t emp . 240 c pea k t emp . 230 c solder i ng ti me 200 c pre h ea ti ng ti me 1 50 c, 9 0 + 30 sec . 2 . 5 c 0 . 5 c/sec . 3 c + 1 c/ C 0 . 5 c ti g ht ty p i cal loose room t empera t ure pre h ea ti ng ra t e 3 c + 1 c/ C 0 . 5 c/sec . re f low h ea ti ng ra t e 2 . 5 c 0 . 5 c/sec . no t e : non -h al i de f lu x s h ould b e used . 2 1 7 c ramp - down 6 c/sec . ma x. ramp - up 3 c/sec . ma x. 1 50 - 200 c * 260 + 0/ - 5 c t 25 c t o pea k 60 t o 1 50 sec . 1 5 sec . ti me w ithi n 5 c of ac t ual pea k t empera t ure t p t s pre h ea t 60 t o 1 80 sec . t l t l t sma x t smin 25 t p ti me t empera t ure no t es : th e ti me f rom 25 c t o pea k t empera t ure = 8 m i nu t es ma x. t sma x = 200 c, t smin = 1 50 c no t e : non -h al i de f lu x s h ould b e used . * recommended pea k t empera t ure f or w i de b od y 400mi l s pac k age i s 245 c
8 all avago data sheets report the creepage and clearance inherent to the optocoupler component itself. these di- mensions are needed as a starting point for the equip- ment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, mini- mum creepage and clearance requirements must be met as speci? ed for individual equipment standards. for insulation and safety related speci? cations parameter symbol value units conditions hcpl- 4504 hcpl- j454 -400e/-600e hcpl-j454 all other options hcpl- 0454 hcnw 4504 minimum external air gap (external clearance) l(101) 7.1 8.0 7.4 4.9 9.6 mm measured from input ter- minals to output terminals, shortest distance through air. minimum external tracking (external creepage) l(102) 7.4 8.0 8.0 4.8 10.0 mm measured from input ter- minals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 0.5 0.5 0.08 1.0 mm through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. minimum internal tracking (internal creepage) na na na na 4.0 mm measured from input ter- minals to output terminals, along internal cavity. tracking resistance (comparative tracking index) cti 175 175 175 175 200 volts din iec 112/vde 0303 part 1 isolation group iiia iiia iiia iiia iiia material group (din vde 0110, 1/89, table 1) creepage, the shortest distance path along the surface of a printed circuit board between the solder ? llets of the input and output leads must be considered. there are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clear- ance distances will also change depending on factors such as pollution degree and insulation level. regulatory information the devices contained in this data sheet have been approved by the following agencies: agency/standard hcpl-4504 hcpl-j454 hcpl-0454 hcnw4504 underwriters laboratories (ul) recognized under ul1577, component recognition program, category fpqu2, file e55361 ul1577 3750 vrms / 1 minute, option 020 5000 vrms / 1 minute 3750 vrms / 1 minute 3750 vrms / 1 minute 5000 vrms / 1 minute canadian standards association (csa) file ca88324 component acceptance notice #5 3750 vrms / 1 minute, option 020 5000 vrms / 1 minute 3750 vrms / 1 minute 3750 vrms / 1 minute 5000 vrms / 1 minute iec/en/din en 60747-5-2 approved under: iec 60747-5-2:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884 teil 2):2003-01 option 060 v iorm = 630 vpeak v iorm = 891 vpeak option 060 v iorm = 560 vpeak v iorm = 1414 vpeak
9 iec/en/din en 60747-5-2 insulation related characteristics description symbol hcpl-0454 hcpl-4504 hcpl-j454 hcnw4504 unit option 060 option 060 installation classi? cation per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms for rated mains voltage 300 v rms for rated mains voltage 450 v rms for rated mains voltage 600 v rms for rated mains voltage 1000 v rms i-iv i-iii i-iv i-iv i-iii i-iv i-iv i-iii i-iii i-iv i-iv i-iv i-iv i-iii climatic classi? cation 55/100/21 55/100/21 55/100/21 55/85/21 pollution degree (din vde 0110/1.89) 2 2 2 2 maximum working insulation voltage v iorm 560 630 891 1414 v peak input to output test voltage, method b* v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc v pr 1050 1181 1670 2652 v peak input to output test voltage, method a* v iorm x 1.5 = v pr , type and sample test, t m = 60 sec, partial discharge < 5 pc v pr 840 945 1336 2121 v peak highest allowable overvoltage* (transient overvoltage, t ini = 10 sec) safety limiting values - maximum values allowed in the event of a failure, also see thermal derating curve v iotm 4000 6000 6000 8000 v peak case temperature t s 150 175 175 150 c input current i s,input 150 230 400 400 ma output power p s,output 600 600 600 700 mw insulation resistance at t s , v io = 500 v r s 10 9 10 9 10 9 10 9 *refer to the optocoupler section of the designer's catalog, under regulatory information (iec/en/din en 60747-5-2) for a detai led description of method a and method b partial discharge test pro? les. note: these optocouplers are suitable for "safe electrical isolation" only within the safety limit data. maintenance of the saf ety data shall be ensured by means of protective circuits. note: insulation characteristics are per iec/en/din en 60747-5-2. note: surface mount classi? cation is class a in accordance with cecc 00802.
10 absolute ma x imum ratings parameter symbol device min . ma x. units note storage temperature t s -55 125 c operating temperature t a hcpl-4504 hcpl-0454 hcpl-j454 -55 100 c hcnw4504 -55 85 average forward input current i f(avg) 25 ma 1 peak forward input current (50% duty cycle, 1 ms pulse width) i f(peak) hcpl-4504 hcpl-0454 50 ma 2 hcpl-j454 hcnw4504 40 peak transient input current (1 s pulse width, 300 pps) i f(trans) hcpl-4504 hcpl-0454 1a hcpl-j454 hcnw4504 0.1 reverse led input voltage (pin 3-2) v r hcpl-4504 hcpl-0454 5v hcpl-j454 hcnw4504 3 input power dissipation p in hcpl-4504 hcpl-0454 45 mw 3 hcpl-j454 hcnw4504 40 average output current (pin 6) i o(avg) 8ma peak output current i o(peak) 16 ma supply voltage (pin 8-5) v cc -0.5 30 v output voltage (pin 6-5) v o -0.5 20 v output power dissipation p o 100 mw 4 lead solder temperature (through-hole parts only) 1.6 mm below seating plane, 10 seconds t ls hcpl-4504 hcpl-j454 260 c up to seating plane, 10 seconds hcnw4504 260 re? ow temperature pro? le t rp hcpl-0454, option 300 , option 500, option 400e & option 600e. see package outline drawings section
11 electrical speci? cations (dc) over recommended temperature (t a = 0c to 70c) unless otherwise speci? ed. see note 12. parameter symbol device min . typ .* ma x. units test conditions fig . note current transfer ratio ctr hcpl-4504 hcpl-0454 25 32 60 % t a = 25c v o = 0.4 v i f = 16 ma, v cc = 4.5 v 1, 2, 4 5 21 34 v o = 0.5 v hcpl-j454 19 37 60 t a = 25c v o = 0.4 v 13 39 v o = 0.5 v hcnw4504 23 29 60 t a = 25c v o = 0.4 v 19 31 63 v o = 0.5 v current transfer ratio ctr hcpl-4504 hcpl-0454 26 35 65 % t a = 25c v o = 0.4 v i f = 12 ma, v cc = 4.5 v 1, 2, 4 5 22 37 v o = 0.5 v hcpl-j454 21 43 65 t a = 25c v o = 0.4 v 16 45 v o = 0.5 v hcnw4504 25 33 65 t a = 25c v o = 0.4 v 21 35 68 v o = 0.5 v logic low output voltage v ol hcpl-4504 hcpl-0454 0.2 0.4 v t a = 25c i o = 4.0 ma i f = 16 ma, v cc = 4.5 v 0.5 i o = 3.3 ma hcpl-j454 0.2 0.4 t a = 25c i o = 3.6 ma 0.5 i o = 3.0 ma hcnw4504 0.2 0.4 t a = 25c i o = 3.6 ma 0.5 i o = 3.0 ma logic high output current i oh 0.003 0.5 a t a = 25c v o = v cc = 5.5 v i f = 0 ma 5 0.01 1 t a = 25c v o = v cc = 15 v 50 logic low supply current i ccl hcpl-4504 hcpl-0454 hcnw4504 50 200 a i f = 16 ma, v o = open, v cc = 15 v 12 hcpl-j454 70 logic high supply current i cch 0.02 1 a t a = 25c i f = 0 ma, v o = open, 12 2v cc = 15 v input forward voltage v f hcpl-4504 hcpl-0454 1.5 1.7 v t a = 25c i f = 16 ma 3 1.8 hcpl-j454 hcnw4504 1.45 1.59 1.85 t a = 25c i f = 16 ma 1.35 1.95 input reverse breakdown voltage bv r hcpl-4504 hcpl-0454 5vi r = 10 a hcpl-j454 hcnw4504 3i r = 100 a temperature coe? cient of forward voltage ?v f ?t a hcpl-4504 hcpl-0454 -1.6 mv/c i f = 16 ma hcpl-j454 hcnw4504 -1.4 input capacitance c in hcpl-4504 hcpl-0454 60 pf f = 1 mhz, v f = 0 v hcpl-j454 hcnw4504 70 *all typicals at t a = 25c.
12 ac switching speci? cations over recommended temperature (t a = 0c to 70c) unless otherwise speci? ed. parameter symbol device min . typ . ma x. units test conditions fig . note propagation delay time to logic low at output t phl 0.2 0.3 s t a = 25c pulse: f = 20 khz, duty cycle = 10%, i f = 16 ma, v cc = 5.0 v, r l = 1.9 k, c l = 15 pf, v thhl = 1.5 v 6, 8, 9 9 0.2 0.5 t phl 0.2 0.5 0.7 s t a = 25c pulse: f = 10 khz, duty cycle = 50%, i f = 12 ma, v cc = 15.0 v, r l = 20 k, c l = 100 pf, v thhl = 1.5 v 6, 10-14 10 hcpl- j454 0.05 1.0 others 0.1 propagation delay time to logic high at output t plh 0.3 0.5 s t a = 25c pulse: f = 20 khz, duty cycle = 10%, i f = 16 ma, v cc = 5.0 v, r l = 1.9 k, c l = 15 pf, v thlh = 1.5 v 6, 8, 9 9 0.3 0.7 t plh 0.3 0.8 1.1 s t a = 25c pulse: f = 10 khz, duty cycle = 50%, i f = 12 ma, v cc = 15.0 v, r l = 20 k, c l = 100 pf, v thlh = 2.0 v 6, 10-14 10 0.2 0.8 1.4 propagation delay di? erence be- tween any 2 parts t plh - t phl -0.4 0.3 0.9 s t a = 25c pulse: f = 10 khz, duty cycle = 50%, i f = 12 ma, v cc = 15.0 v, r l = 20 k, c l = 100 pf, v thhl = 1.5 v, v thlh = 2.0 v 6, 10-14 17 -0.7 0.3 1.3 common mode transient immu- nity at logic high |cm h | 15 30 kv/s t a = 25c v cm = 1500 v p-p v cc = 5.0 v, r l = 1.9 k, c l = 15 pf, i f = 0 ma 7 7, 9 |cm h | 15 30 kv/s v cc = 15.0 v, r l = 20 k, c l = 100 pf, i f = 0 ma 7 8, 10 level output common mode transient immu- nity at logic low level output |cm l | 15 30 kv/s t a = 25c v cm = 1500 v p-p v cc = 5.0 v, r l = 1.9 k, c l = 15 pf, i f = 16 ma 7 7, 9 |cm l | hcpl- j454 15 30 kv/s v cc = 15.0 v, r l = 20 k, c l = 100 pf, i f = 12 ma 7 8, 10 others 10 |cm l | 15 30 kv/s v cc = 15.0 v, r l = 20 k, c l = 100 pf, i f = 16 ma 7 8, 10 *all typicals at t a = 25c.
13 package characteristics over recommended temperature (t a = 0c to 25c) unless otherwise speci? ed. parameter symbol device min . typ .* ma x. units test conditions figure note input-output momentary withstand voltage? v iso hcpl-4504 hcpl-0454 3750 v rms rh 50%, t = 1 min., t a = 25c 6, 13, 16 hcpl-j454 3750 6, 14, 16 hcpl-4504 option 020 5000 6, 11, 15 hcnw4504 5000 6, 15, 16 input-output resistance r i-o hcpl-4504 hcpl-0454 hcpl-j454 10 12 v i-o = 500 vdc 6 hcnw4504 10 12 10 13 t a = 25c 10 11 t a = 100c capacitance (input-output) c i-o hcpl-4504 hcpl-0454 0.6 pf f = 1 mhz 6 hcpl-j454 0.8 hcnw4504 0.5 0.6 all typicals at t a = 25c.. ?the input-output momentary withstand voltage is a dielectric v oltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to the iec/en/din en 60747-5-2 insulation related characteristics table (if applicable), your equipment level safety speci? cation or avago application note 1074 entitled optocoupler input-output endurance voltage. notes : 1. derate linearly above 70c free-air temperature at a rate of 0.8 ma/c (8-pin dip). derate linearly above 85c free-air temperature at a rate of 0.5 ma/c (so-8). 2. derate linearly above 70c free-air temperature at a rate of 1.6 ma/c (8-pin dip). derate linearly above 85c free-air temperature at a rate of 1.0 ma/c (so-8). 3. derate linearly above 70c free-air temperature at a rate of 0.9 mw/c (8-pin dip). derate linearly above 85c free-air temperature at a rate of 1.1 mw/c (so-8). 4. derate linearly above 70c free-air temperature at a rate of 2.0 mw/c (8-pin dip). derate linearly above 85c free-air temperature at a rate of 2.3 mw/c (so-8). 5. current transfer ratio in percent is de? ned as the ratio of output collector current, i o , to the forward led input current, i f , times 100. 6. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 7. under ttl load and drive conditions: common mode transient immunity in a logic high level is the maximum tolerable (positive ) dv cm /dt on the leading edge of the common mode pulse, v cm , to assure that the output will remain in a logic high state (i.e., v o > 2.0 v). common mode transient immunity in a logic low level is the maximum tolerable (negative) dv cm /dt on the trailing edge of the common mode pulse signal, v cm , to assure that the output will remain in a logic low state (i.e., v o < 0.8 v). 8. under ipm (intelligent power module) load and led drive conditions: common mode transient immunity in a logic high level is the maximum tolerable dv cm /dt on the leading edge of the common mode pulse, v cm , to assure that the output will remain in a logic high state (i.e., v o > 3.0 v). common mode transient immunity in a logic low level is the maximum tolerable dv cm /dt on the trailing edge of the common mode pulse signal, v cm , to assure that the output will remain in a logic low state (i.e., v o < 1.0 v). 9. the 1.9 k load represents 1 ttl unit load of 1.6 ma and the 5.6 k pull-up resistor. 10. the r l = 20 k, c l = 100 pf load represents an ipm (intelligent power module) load. 11. see option 020 data sheet for more information. 12. use of a 0.1 f bypass capacitor connected between pins 5 and 8 is recommended. 13. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 4500 v rms for 1 seco nd (leakage detection current limit, i i-o 5 a). 14. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 4500 v rms for 1 seco nd (leakage detection current limit, i i-o 5 a). 15. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 6000 v rms for 1 seco nd (leakage detection current limit, i i-o 5 a). 16. this test is performed before the 100% production test shown in the vde 0884 insulation related characteristics table, if applicable. 17. the di? erence between t plh and t phl between any two devices (same part number) under the same test condition. (see power inverter dead time and propagation delay speci? cations section.)
14 figure 1 . dc and pulsed transfer characteristics . figure 2 . current transfer ratio vs . input current . figure 3 . input current vs . forward voltage . 0 10 20 v o ?output voltage ?v i o ?output current ?ma 10 5 0 t = 25? v = 5.0 v a cc 40 ma 35 ma 30 ma 25 ma 20 ma 15 ma 10 ma i = 5 ma f hcpl-4504/0454 i o ?output current ?ma 0 0 v o ?output voltage ?v 20 15 25 5 510 20 15 10 t a = 25?c v cc = 5.0 v 40 ma 30 ma 35 ma 25 ma 15 ma 20 ma 10 ma i f = 5 ma hcpl-j454 0 10 20 v o ?output voltage ?v i o ?output current ?ma 20 10 0 t = 25? v = 5.0 v a cc 40 ma 35 ma 30 ma 25 ma 20 ma 15 ma 10 ma i = 5 ma f hcnw4504 2 4 6 8 12 14 16 18 i f ?input current ?ma normalized current transfer ratio 1.5 1.0 0.5 0.0 2 4 6 8 10 12 14 16 18 0 20 22 24 26 i f = 16 ma v o = 0.4 v v cc = 5.0 v t a = 25? normalized hcpl-4504/0454 normalized current transfer ratio 0 0 i f ?input current ?ma 20 15 2.0 0.5 510 1.5 1.0 25 normalized i f = 16 ma v o = 0.4 v v cc = 5.0 v t a = 25?c hcpl-j454 i f ?input current ?ma normalized current transfer ratio 1.6 0.8 0 51015 0 20 25 i f = 16 ma v o = 0.4 v v cc = 5.0 v t a = 25? normalized hcnw4504 0.4 1.2 2.0 v f ?forward voltage ?volts 100 10 0.1 0.01 1.1 1.2 1.3 1.4 i f ?forward current ?ma 1.6 1.5 1.0 0.001 1000 i f v f + t = 25? a hcpl-4504/0454 v f ?forward voltage ?volts 100 10 0.1 0.01 1.2 1.3 1.4 1.5 i f ?forward current ?ma 1.7 1.6 1.0 0.001 1000 i f v f + t = 25? a hcpl-j454/hcnw4504
15 figure 6 . switching test circuit . figure 4 . current transfer ratio vs . temperature . figure 5 . logic high output current vs . temperature . figure 7 . test circuit for transient immunity and typical waveforms . t a ?temperature ?? normalized current transfer ratio 1.0 0.8 0.6 1.1 0.7 0.9 -40 -20 0 20 40 60 80 100 120 -60 i f = 16 ma v o = 0.4 v v cc = 5.0 v t a = 25? normalized hcpl-4504/0454 normalized current transfer ratio -60 0.85 t a ?temperature ?? 100 60 1.05 0.9 -20 20 1.0 0.95 normalized i f = 16 ma v o = 0.4 v v cc = 5.0 v t a = 25?c 80 40 0 -40 hcpl-j454 t a ?temperature ?? normalized current transfer ratio 1.0 0.9 0.85 1.05 0.95 -40 -20 0 20 40 60 80 100 120 -60 i f = 16 ma v o = 0.4 v v cc = 5.0 v t a = 25? normalized hcnw4504 t a ?temperature ?? i oh ?logic high output current ?na 10 4 10 3 10 2 10 1 10 0 10 -1 10 -2 -40 -20 0 20 40 60 80 100 120 -60 i f = 0 ma v o = v cc = 5.0 v v o pulse gen. z = 50 t = 5 ns o r i monitor f i f 0.1? l r c l r m 0 t phl t plh o v i f ol v thhl v thlh v v cc v cc 1 2 3 4 8 7 6 5 v o i f 0.1? l r a b pulse gen. v cm + v ff l c o v ol v o v 0 v 10% 90% 90% 10% switch at a: i = 0 ma f switch at b: i = 12 ma, 16 ma f cm v t r t f cc v v cc 1 2 3 4 8 7 6 5
16 figure 11 . propagation delay time vs . temperature . figure 8 . propagation delay time vs . temperature . figure 10 . propagation delay time vs . load resistance . figure 9. propagation delay time vs . load resis- tance . t a ?temperature ?? t p ?propagation delay ?? 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 -40 -20 0 20 40 60 80 100 120 -60 v cc = 5.0 v r l = 1.9 k c l = 15 pf v thhl t plh t phl i f = 10 ma i f = 16 ma = v thlh = 1.5 v 10% duty cycle hcpl-4504/0454 t a ?temperature ?? t p ?propagation delay ?? 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 -40 -20 0 20 40 60 80 100 120 -60 v cc = 5.0 v r l = 1.9 k c l = 15 pf v thhl t plh t phl i f = 10 ma i f = 16 ma = v thlh = 1.5 v 10% duty cycle hcpl-j454/hcnw4504 r l ?load resistance ?k t p ?propagation delay ?? 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2 4 6 8 10 12 14 16 18 0 20 t phl v cc = 5.0 v t a = 25?c c l = 15 pf v = v = 1.5 v i f = 10 ma i f = 16 ma t plh 10% duty cycle thhl thlh r l ?load resistance ?k t p ?propagation delay ?? 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2 4 6 8 10 12 14 16 18 0 20 1.6 1.8 2.0 2.2 2.4 2.6 v cc = 5.0 v t a = 25?c c l = 100 pf v thhl = 1.5 v v thlh = 2.0 v i f = 10 ma i f = 16 ma t plh t phl 50% duty cycle t a ?temperature ?? t p ?propagation delay ?? 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 -40 -20 0 20 40 60 80 100 120 -60 v cc = 15.0 v r l = 20 k c l = 100 pf v thhl = 1.5 v v thlh = 2.0 v t plh t phl i f = 10 ma i f = 16 ma 50% duty cycle hcpl-4504/0454 t a ?temperature ?? t p ?propagation delay ?? 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 -40 -20 0 20 40 60 80 100 120 -60 v cc = 15.0 v r l = 20 k c l = 100 pf v thhl = 1.5 v v thlh = 2.0 v t plh t phl i f = 10 ma i f = 16 ma 50% duty cycle hcpl-j454/hcnw4504 figure 14 . propagation delay time vs . supply voltage . figure 13 . propagation delay time vs . load capacitance . figure 12 . propagation delay time vs . load resistance . r l ?load resistance ?k t p ?propagation delay ?? 1.6 1.4 1.2 1.0 0.6 0.2 0.0 5 1015202530354045 0 v cc = 15.0 v t a = 25?c c l = 100 pf v thhl = 1.5 v v thlh = 2.0 v 50 t plh t phl 1.8 0.4 0.8 i f = 10 ma i f = 16 ma 50% duty cycle c l ?load capacitance ?pf t p ?propagation delay ?? 2.0 1.5 0.5 0.0 100 200 300 400 500 600 700 800 900 0 v cc = 15.0 v t a = 25?c r l = 20 k v thhl = 1.5 v v thlh = 2.0 v 1000 t plh t phl 2.5 3.0 3.5 1.0 i f = 10 ma i f = 16 ma 50% duty cycle v cc ?supply voltage ?v tp ?propagation delay ?? 0.9 0.8 0.6 0.2 11 12 13 14 15 16 17 18 19 10 20 1.0 1.1 1.2 0.7 t a = 25?c r l = 20 k c l = 100 pf v v 0.5 0.4 0.3 t plh t phl i f = 10 ma i f = 16 ma 50% duty cycle thhl = 1.5 v = 2.0 v thlh
17 figure 15 . thermal derating curve, dependence of safety limiting valve with case temperature per iec/en/din en 60747-5-2 . output power ?p s , input current ?i s 0 0 t s ?case temperature ?? 200 50 400 125 25 75 100 150 600 800 200 100 300 500 700 hcpl-4504 option 060/hcpl-j454 175 (230) p s (mw) i s (ma) for hcpl-4504 option 060 i s (ma) for hcpl-j454 output power ?p s , input current ?i s 0 0 t s ?case temperature ?? 175 1000 50 400 125 25 75 100 150 600 800 200 100 300 500 700 900 hcpl-0454 option 060/hcnw4504 p s (mw) for hcnw4504 i s (ma) for hcnw4504 p s (mw) for hcpl-0454 option 060 i s (ma) for hcpl-0454 option 060 (150) figure 16 . typical power inverter . base/gate drive circuit hcpl-4504/0454/j454 hcnw4504 2 3 8 7 6 5 +hv q1 led 1 out 1 base/gate drive circuit 2 3 8 7 6 5 ?v q2 led 2 out 2 + + hcpl-4504/0454/j454 hcnw4504
18 power inverter dead time and propagation delay speci? ca- tions the hcpl-4504/0454/j454 and hcnw4504 include a speci? ca tion intended to help designers minimize dead time in their power inverter designs. the new propaga- tion delay di? erence speci? cation (t plh - t phl ) is useful for deter min ing not only how much optocoupler switch- ing delay is needed to prevent shoot-through current, but also for determin ing the best achievable worst-case dead time for a given design. when inverter power transis tors switch (q1 and q2 in figure 17), it is essential that they never conduct at the same time. extremely large currents will ? ow if there is any overlap in their conduction during switching tran- sitions, poten tially damaging the transistors and even the sur rounding circuitry. this shoot-through current is eliminated by delay ing the turn-on of one transistor (q2) long enough to ensure that the opposing transistor (q1) has completely turned o? . this delay intro duces a small amount of dead time at the output of the inverter dur- ing which both transistors are o? during switching tran- sitions. minimiz ing this dead time is an important design goal for an inverter designer. the amount of turn-on delay needed depends on the propa ga tion delay characteristics of the optocoupler, as well as the characteristics of the transistor base/gate drive circuit. consid er ing only the delay characteris tics of the optocoupler (the charac teristics of the base/gate drive circuit can be analyzed in the same way), it is important to know the minimum and maximum turn-on (t phl ) and turno? (t plh ) propagation delay speci? ca tions, prefer- ably over the desired operating t emperature range. the importance of these speci? cations is illustrated in figure 17. the waveforms labeled led1, led2, out1, and out2 are the input and output voltages of the opto- coupler circuits driving q1 and q2 respectively. most in- verters are designed such that the power transistor turns on when the optocoupler led turns on; this ensures that both power transistors will be o? in the event of a power loss in the control circuit. inverters can also be designed such that the power transistor turns o? when the opto- coupler led turns on; this type of design, however, re- quires additional fail-safe circuitry to turn o? the power transistor if an over-current condition is detected. the timing illustrated in figure 17 assumes that the power transistor turns on when the optocoupler led turns on. figure 17 . led delay and dead time diagram .
for product information and a complete list of distributors, please go to our website: www . avagotech . com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2009 avago technologies. all rights reserved. obsoletes av01-0552en av02-0867en - january 4, 2010 this expression can be rearranged to obtain [(t plhmax -t phlmin )-(t phlmin -t phlmax )], and further rearranged to obtain [(t plh -t phl ) max -(t plh -t phl ) min ], which is the maximum minus the minimum data sheet values of (t plh -t phl ). the di? erence between the maxi- mum and minimum values depends directly on the total spread in propagation delays and sets the limit on how good the worst-case dead time can be for a given design. therefore, opto coup lers with tight propagation delay speci? cations (and not just shorter delays or lower pulse- width distortion) can achieve short dead times in power inverters. the hcpl-4504/0454/j454 and hcnw4504 specify a minimum (t plh - t phl ) of -0.7 s over an operat- ing temperature range of 0-70c, resulting in a maximum dead time of 2.0 s when the led turn-on delay is equal to (t plh -t phl ) max , or 1.3 s. it is important to maintain accurate led turn-on delays because delays shorter than (t plh - t phl ) max may allow shoot-through currents, while longer delays will increase the worst-case dead time. the led signal to turn on q2 should be delayed enough so that an optocoupler with the very fastest turn-on propagation delay (t phlmin ) will never turn on before an optocoupler with the very slowest turn-o? propagation delay (t plhmax ) turns o? . to ensure this, the turn-on of the optocoupler should be delayed by an amount no less than (t plhmax - t phlmin ), which also happens to be the max- imum data sheet value for the propagation delay di? er- ence speci? cation, (t plh - t phl ). the hcpl-4504/0454/j454 and hcnw4504 specify a maxi mum (t plh - t phl ) of 1.3 s over an operating temper ature range of 0-70c. although (t plh -t phl ) max tells the designer how much delay is needed to prevent shoot-through current, it is insu? - cient to tell the designer how much dead time a design will have. assuming that the optocoupler turn-on delay is exactly equal to (t plh - t phl ) max , the minimum dead time is zero (i.e., there is zero time between the turno? of the very slowest optocoupler and the turn-on of the very fastest optocoupler). calculating the maximum dead time is slightly more compli cated. assuming that the led turn-on delay is still exactly equal to (t plh - t phl ) max , it can be seen in figure 17 that the maximum dead time is the sum of the maximum di? erence in turn-on delay plus the maxi mum di? erence in turno? delay, [(t plhmax -t plhmin )+(t phlmax -t phlmin )].

▲Up To Search▲

Price & Availability of HCPL-J454-400E

	To Download HCPL-J454-400E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .